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december 1988 order number: 231468-003 8259A programmable interrupt controller (8259A/8259A-2) y 8086, 8088 compatible y mcs-80, mcs-85 compatible y eight-level priority controller y expandable to 64 levels y programmable interrupt modes y individual request mask capability y single a 5v supply (no clocks) y available in 28-pin dip and 28-lead plcc package (see packaging spec., order y 231369) y available in express e standard temperature range e extended temperature range the intel 8259A programmable interrupt controller handles up to eight vectored priority interrupts for the cpu. it is cascadable for up to 64 vectored priority interrupts without additional circuitry. it is packaged in a 28-pin dip, uses nmos technology and requires a single a 5v supply. circuitry is static, requiring no clock input. the 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter- rupts. it has several modes, permitting optimization for a variety of system requirements. the 8259A is fully upward compatible with the intel 8259. software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (mcs-80/85, non-buffered, edge triggered). 231468 1 figure 1. block diagram dip 231468 2 plcc 231468 31 figure 2. pin configurations
8259A table 1. pin description symbol pin no. type name and function v cc 28 i supply: a 5v supply. gnd 14 i ground cs 1i chip select: a low on this pin enables rd and wr communication between the cpu and the 8259A. inta functions are independent of cs. wr 2i write: a low on this pin when cs is low enables the 8259A to accept command words from the cpu. rd 3i read: a low on this pin when cs is low enables the 8259A to release status onto the data bus for the cpu. d 7 d 0 411 i/o bidirectional data bus: control, status and interrupt-vector information is transferred via this bus. cas 0 cas 2 12, 13, 15 i/o cascade lines: the cas lines form a private 8259A bus to control a multiple 8259A structure. these pins are outputs for a master 8259A and inputs for a slave 8259A. sp /en 16 i/o slave program/enable buffer: this is a dual function pin. when in the buffered mode it can be used as an output to control buffer transceivers (en). when not in the buffered mode it is used as an input to designate a master (sp e 1) or slave (sp e 0). int 17 o interrupt: this pin goes high whenever a valid interrupt request is asserted. it is used to interrupt the cpu, thus it is connected to the cpu's interrupt pin. ir 0 ir 7 1825 i interrupt requests: asynchronous inputs. an interrupt request is executed by raising an ir input (low to high), and holding it high until it is acknowledged (edge triggered mode), or just by a high level on an ir input (level triggered mode). inta 26 i interrupt acknowledge: this pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the cpu. a 0 27 i ao address line: this pin acts in conjunction with the cs ,wr , and rd pins. it is used by the 8259A to decipher various command words the cpu writes and status the cpu wishes to read. it is typically connected to the cpu a0 address line (a1 for 8086, 8088). 2
8259A functional description interrupts in microcomputer systems microcomputer system design requires that i.o de- vices such as keyboards, displays, sensors and oth- er components receive servicing in a an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on throughput. the most common method of servicing such devic- es is the polled approach. this is where the proces- sor must test each device in sequence and in effect ``ask'' each one if it needs servicing. it is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system throughput, thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices. a more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. in effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. once this servicing is com- plete, however, the processor would resume exactly where it left off. this method is called interrupt . it is easy to see that system throughput would drastically increase, and thus more tasks could be assumed by the micro- computer to further enhance its cost effectiveness. the programmable interrupt controller (pic) func- tions as an overall manager in an interrupt-driven system environment. it accepts requests from the peripheral equipment, determines which of the in- coming requests is of the highest importance (priori- ty), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the cpu based on this determination. each peripheral device or structure usually has a special program or ``routine'' that is associated with its specific functional or operational requirements; this is referred to as a ``service routine''. the pic, after issuing an interrupt to the cpu, must somehow input information into the cpu that can ``point'' the program counter to the service routine associated with the requesting device. this ``pointer'' is an ad- dress in a vectoring table and will often be referred to, in this document, as vectoring data. 231468 3 figure 3a. polled method 231468 4 figure 3b. interrupt method 3
8259A the 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems. it manages eight levels or requests and has built-in features for expandability to other 8259A's (up to 64 levels). it is programmed by the system's software as an i/o peripheral. a selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements. the priority modes can be changed or reconfigured dynamically at any time during the main program. this means that the complete interrupt structure can be defined as required, based on the total system environment. interrupt request register (irr) and in-service register (isr) the interrupts at the ir input lines are handled by two registers in cascade, the interrupt request reg- ister (irr) and the in-service (isr). the irr is used to store all the interrupt levels which are requesting service; and the isr is used to store all the interrupt levels which are being serviced. priority resolver this logic block determines the priorites of the bits set in the irr. the highest priority is selected and strobed into the corresponding bit of the isr during inta pulse. interrupt mask register (imr) the imr stores the bits which mask the interrupt lines to be masked. the imr operates on the irr. masking of a higher priority input will not affect the interrupt request lines of lower quality. int (interrupt) this output goes directly to the cpu interrupt input. the v oh level on this line is designed to be fully compatible with the 8080a, 8085a and 8086 input levels. inta (interrupt acknowledge) inta pulses will cause the 8259A to release vector- ing information onto the data bus. the format of this data depends on the system mode ( m pm) of the 8259A. data bus buffer this 3-state, bidirectional 8-bit buffer is used to inter- face the 8259A to the system data bus. control words and status information are transferred through the data bus buffer. read/write control logic the function of this block is to accept output com- mands from the cpu. it contains the initialization command word (icw) registers and operation command word (ocw) registers which store the various control formats for device operation. this function block also allows the status of the 8259A to be transferred onto the data bus. cs (chip select) a low on this input enables the 8259A. no reading or writing of the chip will occur unless the device is selected. wr (write) a low on this input enables the cpu to write con- trol words (icws and ocws) to the 8259A. rd (read) a low on this input enables the 8259A to send the status of the interrupt request register (irr), in service register (isr), the interrupt mask register (imr), or the interrupt level onto the data bus. a 0 this input signal is used in conjunction with wr and rd signals to write commands into the various com- mand registers, as well as reading the various status registers of the chip. this line can be tied directly to one of the address lines. 4
8259A 231468 5 figure 4a. 8259A block diagram 5
8259A 231468 6 figure 4b. 8259A block diagram 6
8259A the cascade buffer/comparator this function block stores and compares the ids of all 8259A's used in the system. the associated three i/o pins (cas0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. as a master, the 8259A sends the id of the interrupting slave device onto the cas0 2 lines. the slave thus selected will send its preprogrammed subroutine address onto the data bus during the next one or two consecutive inta pulses. (see section ``cascading the 8259A''.) interrupt sequence the powerful features of the 8259A in a microcom- puter system are its programmability and the inter- rupt routine addressing capability. the latter allows direct or indirect jumping to the specific interrupt rou- tine requested without any polling of the interrupting devices. the normal sequence of events during an interrupt depends on the type of cpu being used. the events occur as follows in an mcs-80/85 sys- tem: 1. one or more of the interrupt request lines (ir7 0) are raised high, setting the correspond- ing irr bit(s). 2. the 8259A evaluates these requests, and sends an int to the cpu, if appropriate. 3. the cpu acknowledges the int and responds with an inta pulse. 4. upon receiving an inta from the cpu group, the highest priority isr bit is set, and the correspond- ing irr bit is reset. the 8259A will also release a call instruction code (11001101) onto the 8-bit data bus through its d7 0 pins. 5. this call instruction will initiate two more inta pulses to be sent to the 8259A from the cpu group. 6. these two inta pulses allow the 8259A to re- lease its preprogrammed subroutine address onto the data bus. the lower 8-bit address is re- leased at the first inta pulse and the higher 8-bit address is released at the second inta pulse. 7. this completes the 3-byte call instruction re- leased by the 8259A. in the aeoi mode the isr bit is reset at the end of the third inta pulse. otherwise, the isr bit remains set until an appro- priate eoi command is issued at the end of the interrupt sequence. the events occuring in an 8086 system are the same until step 4. 4. upon receiving an inta from the cpu group, the highest priority isr bit is set and the correspond- ing irr bit is reset. the 8259A does not drive the data bus during this cycle. 5. the 8086 will initiate a second inta pulse. dur- ing this pulse, the 8259A releases an 8-bit pointer onto the data bus where it is read by the cpu. 6. this completes the interrupt cycle. in the aeoi mode the isr bit is reset at the end of the sec- ond inta pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. if no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. both the vectoring bytes and the cas lines will look like an interrupt level 7 was requested. when the 8259A pic receives an interrupt, int be- comes active and an interrupt acknowledge cycle is started. if a higher priority interrupt occurs between the two inta pulses, the int line goes inactive im- mediately after the second inta pulse. after an un- specified amount of time the int line is activated again to signify the higher priority interrupt waiting for service. this inactive time is not specified and can vary between parts. the designer should be aware of this consideration when designing a sys- tem which uses the 8259A. it is recommended that proper asynchronous design techniques be fol- lowed. 7
8259A 231468 7 figure 4c. 8259A block diagram 231468 8 figure 5. 8259A interface to standard system bus interrupt sequence outputs mcs-80, mcs-85 this sequence is timed by three inta pulses. during the first inta pulse the call opcode is enabled onto the data bus. content of first interrupt vector byte d7 d6 d5 d4 d3 d2 d1 d0 call code 1 1 0 0 1 1 0 1 during the second inta pulse the lower address of the appropriate service routine is enabled onto the data bus. when interval e 4 bits a 5 a 7 are pro- grammed, while a 0 a 4 are automatically inserted by the 8259A. when interval e 8 only a 6 and a 7 are programmed, while a 0 a 5 are automatically insert- ed. 8
8259A content of second interrupt vector byte ir interval e 4 d7 d6 d5 d4 d3 d2 d1 d0 7a7a6a511100 6a7a6a511000 5a7a6a510100 4a7a6a510000 3a7a6a501100 2a7a6a501000 1a7a6a500100 0a7a6a500000 ir interval e 8 d7 d6 d5 d4 d3 d2 d1 d0 7a7a6111000 6a7a6110000 5a7a6101000 4a7a6100000 3a7a6011000 2a7a6010000 1a7a6001000 0a7a6000000 during the third inta pulse the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (a 8 a 15 ), is enabled onto the bus. content of third interrupt vector byte d7 d6 d5 d4 d3 d2 d1 d0 a15 a14 a13 a12 a11 a10 a9 a8 8086, 8088 8086 mode is similar to mcs-80 mode except that only two interrupt acknowledge cycles are issued by the processor and no call opcode is sent to the processor. the first interrupt acknowledge cycle is similar to that of mcs-80, 85 systems in that the 8259A uses it to internally freeze the state of the interrupts for priority resolution and as a master it issues the interrupt code on the cascade lines at the end of the inta pulse. on this first cycle it does not issue any data to the processor and leaves its data bus buffers disabled. on the second interrupt ac- knowledge cycle in 8086 mode the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code composed as follows (note the state of the adi mode control is ignored and a 5 a 11 are unused in 8086 mode): content of interrupt vector byte for 8086 system mode d7 d6 d5 d4 d3 d2 d1 d0 ir7 t7 t6 t5 t4 t3 1 1 1 ir6 t7 t6 t5 t4 t3 1 1 0 ir5 t7 t6 t5 t4 t3 1 0 1 ir4 t7 t6 t5 t4 t3 1 0 0 ir3 t7 t6 t5 t4 t3 0 1 1 ir2 t7 t6 t5 t4 t3 0 1 0 ir1 t7 t6 t5 t4 t3 0 0 1 ir0 t7 t6 t5 t4 t3 0 0 0 programming the 8259A the 8259A accepts two types of command words generated by the cpu: 1. initialization command words (icws): before normal operation can begin, each 8259A in the system must be brought to a starting pointeby a sequence of 2 to 4 bytes timed by wr pulses. 2. operation command words (ocws): these are the command words which command the 8259A to operate in various interrupt modes. these modes are: a. fully nested mode b. rotating priority mode c. special mask mode d. polled mode the ocws can be written into the 8259A anytime after initialization. initialization command words (icws) general whenever a command is issued with a0 e 0 and d4 e 1, this is interpreted as initialization command word 1 (icw1). icw1 starts the intiitalization se- quence during which the following automatically oc- cur. a. the edge sense circuit is reset, which means that following initialization, an interrupt request (ir) in- put must make a low-to-high transistion to gener- ate an interrupt. 9
8259A b. the interrupt mask register is cleared. c. ir7 input is assigned priority 7. d. the slave mode address is set to 7. e. special mask mode is cleared and status read is set to irr. f. if ic4 e 0, then all functions selected in icw4 are set to zero. (non-buffered mode * , no auto- eoi, mcs-80, 85 system). * note: master/slave in icw4 is only used in the buffered mode. initialization command words 1 and 2 (icw1, icw2) a 5 a 15 : page starting address of service routines . in an mcs 80/85 system, the 8 request levels will generate calls to 8 locations equally spaced in memory. these can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 rou- tines will occupy a page of 32 or 64 bytes, respec- tively. the address format is 2 bytes long (a 0 a 15 ). when the routine interval is 4, a 0 a 4 are automatically in- serted by the 8259A, while a 5 a 15 are programmed externally. when the routine interval is 8, a 0 a 5 are automatically inserted by the 8259A, while a 6 a 15 are programmed externally. the 8-byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table. in an 8086 system a 15 a 11 are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level. a 10 a 5 are ignored and adi (address interval) has no effect. ltim: if ltim e 1, then the 8259A will operate in the level interrupt mode. edge detect logic on the interrupt inputs will be disabled. adi: call address interval. adi e 1 then inter- val e 4; adi e 0 then interval e 8. sngl: single. means that this is the only 8259A in the system. if sngl e 1 no icw3 will be issued. ic4: if this bit is seteicw4 has to be read. if icw4 is not needed, set ic4 e 0. initialization command word 3 (icw3) this word is read only when there is more than one 8259A in the system and cascading is used, in which case sngl e 0. it will load the 8-bit slave register. the functions of this register are: a. in the master mode (either when sp e 1, or in buffered mode when m/s e 1 in icw4) a ``1'' is set for each slave in the system. the master then will release byte 1 of the call sequence (for mcs- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines. b. in the slave mode (either when sp e 0, or if buf e 1 and m/s e 0 in icw4) bits 2 0 identify the slave. the slave compares its cascade input with these bits and, if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it on the data bus. 231468 9 figure 6. initialization sequence 10
8259A initialization command word 4 (icw4) sfnm: if sfnm e 1 the special fully nested mode is programmed. buf: if buf e 1 the buffered mode is pro- grammed. in buffered mode sp /en be- comes an enable output and the master/ slave determination is by m/s. m/s: if buffered mode is selected: m/s e 1 means the 8259A is programmed to be a master, m/s e 0 means the 8259A is pro- grammed to be a slave. if buf e 0, m/s has no function. aeoi: if aeoi e 1 the automatic end of interrupt mode is programmed. m pm: microprocessor mode: m pm e 0 sets the 8259A for mcs-80, 85 system operation, m pm e 1 sets the 8259A for 8086 system operation. 231468 10 231468 11 figure 7. initialization command word format 11
8259A 231468 12 231468 13 231468 14 note: slave id is equal to the corresponding master ir input. figure 7. initialization command word format (continued) 12
8259A operation command words (ocws) after the initialization command words (icws) are programmed into the 8259A, the chip is ready to ac- cept interrupt requests at its input lines. however, during the 8259A operation, a selection of algo- rithms can command the 8259A to operate in vari- ous modes through the operation command words (ocws). operation control words (ocws) ocw1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 m7 m6 m5 m4m3m2m1 m0 ocw2 0 r sl eoi 0 0 l2 l1 l0 ocw3 0 0 esmm smm 0 1 p rr ris 231468 15 231468 16 figure 8. operation command word format 13
8259A operation control word 1 (ocw1) ocw1 sets and clears the mask bits in the interrupt mask register (imr). m 7 m 0 represent the eight mask bits. m e 1 indicates the channel is masked (inhibited), m e 0 indicates the channel is enabled. operation control word 2 (ocw2) r, sl, eoiethese three bits control the rotate and end of interrupt modes and combinations of the two. a chart of these combinations can be found on the operation command word format. l 2 ,l 1 ,l 0 ethese bits determine the interrupt level acted upon when the sl bit is active. 231468 17 figure 8. operation command word format (continued) 14
8259A operation control word 3 (ocw3) esmmeenable special mask mode. when this bit is set to 1 it enables the smm bit to set or reset the special mask mode. when esmm e 0 the smm bit becomes a ``don't care''. smmespecial mask mode. if esmm e 1 and smm e 1 the 8259A will enter special mask mode. if esmm e 1 and smm e 0 the 8259A will revert to normal mask mode. when esmm e 0, smm has no effect. fully nested mode this mode is entered after initialization unless anoth- er mode is programmed. the interrupt requests are ordered in priority from 0 through 7 (0 highest). when an interrupt is acknowledged the highest pri- ority request is determined and its vector placed on the bus. additionally, a bit of the interrupt service register (iso-7) is set. this bit remains set until the microprocessor issues an end of interrupt (eoi) command immediately before returning from the service routine, or if aeoi (automatic end of inter- rupt) bit is set, until the trailing edge of the last inta. while the is bit is set, all further interrupts of the same or lower priority are inhibited, while higher lev- els will generate an interrupt (which will be acknowl- edged only if the microprocessor internal interupt enable flip-flop has been re-enabled through soft- ware). after the initialization sequence, ir0 has the highest prioirity and ir7 the lowest. priorities can be changed, as will be explained, in the rotating priority mode. end of interrupt (eoi) the in service (is) bit can be reset either automati- cally following the trailing edge of the last in se- quence inta pulse (when aeoi bit in icw1 is set) or by a command word that must be issued to the 8259A before returning from a service routine (eoi command). an eoi command must be issued twice if in the cascade mode, once for the master and once for the corresponding slave. there are two forms of eoi command: specific and non-specific. when the 8259A is operated in modes which perserve the fully nested structure, it can de- termine which is bit to reset on eoi. when a non- specific eoi command is issued the 8259A will auto- matically reset the highest is bit of those that are set, since in the fully nested mode the highest is level was necessarily the last level acknowledged and serviced. a non-specific eoi can be issued with ocw2 (eoi e 1, sl e 0, r e 0). when a mode is used which may disturb the fully nested structure, the 8259A may no longer be able to determine the last level acknowledged. in this case a specific end of interrupt must be issued which includes as part of the command the is level to be reset. a specific eoi can be issued with ocw2 (eoi e 1, sl e 1, r e 0, and l0 l2 is the binary level of the is bit to be reset). it should be noted that an is bit that is masked by an imr bit will not be cleared by a non-specific eoi if the 8259A is in the special mask mode. automatic end of interrupt (aeoi) mode if aeoi e 1 in icw4, then the 8259A will operate in aeoi mode continuously until reprogrammed by icw4. in this mode the 8259A will automatically per- form a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in mcs-80/85, second in 8086). note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single 8259A. the aeoi mode can only be used in a master 8259A and not a slave. 8259As with a copyright date of 1985 or later will operate in the aeoi mode as a master or a slave. automatic rotation (equal priority devices) in some applications there are a number of interrupt- ing devices of equal priority. in this mode a device, after being serviced, receives the lowest priority, so a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once . for example, if the priority and ``in service'' status is: before rotate (ir4 the highest prioirity requiring service) ``is'' status 231468 18 priority status 231468 19 15
8259A after rotate (ir4 was serviced, all other priorities rotated correspondingly) ``is'' status 231468 20 priority status 231468 21 there are two ways to accomplish automatic rota- tion using ocw2, the rotation on non-specific eoi command (r e 1, sl e 0, eoi e 1) and the ro- tate in automatic eoi mode which is set by (r e 1, sl e 0, eoi e 0) and cleared by (r e 0, sl e 0, eoi e 0). specific rotation (specific priority) the programmer can change priorities by program- ming the bottom priority and thus fixing all other pri- orities; i.e., if ir5 is programmed as the bottom prior- ity device, then ir6 will have the highest one. the set priority command is issued in ocw2 where: r e 1, sl e 1, l0 l2 is the binary priority level code of the bottom priority device. observe that in this mode internal status is updated by software control during ocw2. however, it is in- dependent of the end of interrupt (eoi) command (also executed by ocw2). priority changes can be executed during an eoi command by using the ro- tate on specific eoi command in ocw2 (r e 1, sl e 1, eoi e 1 and lo l2 e ir level to receive bottom priority). interrupt masks each interrupt request input can bem masked indi- vidually by the interrupt mask register (imr) pro- grammed through ocw1. each bit in the imr masks one interrupt channel if it is set (1). bit 0 masks ir0, bit 1 masks ir1 and so forth. masking an ir channel does not affect the other channels operation. special mask mode some applications may require an interrupt service routine to dynamically alter the system priority struc- ture during its execution under software control. for example, the routine may wish to inhibit lower priori- ty requests for a portion of its execution but enable some of them for another portion. the difficulty here is that if an interrupt request is acknowledged and an end of interrupt command did not reset its is bit (i.e., while executing a service routine), the 8259A would have inhibited all lower priority requests with no easy way for the routine to enable them. that is where the special mask mode comes in. in the special mask mode, when a mask bit is set in ocw1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. thus, any interrupts may be selectively enabled by loading the mask register. the special mask mode is set by owc3 where: ssmm e 1, smm e 1, and cleared where ssmm e 1, smm e 0. poll command in poll mode the int output functions as it normally does. the microprocessor should ignore this output. this can be accomplished either by not connecting the int output or by masking interrupts within the microprocessor, thereby disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p e `1'' in ocw3. the 8259A treats the next rd pulse to the 8259A (i.e., rd e 0, cs e 0) as an interrupt ac- knowledge, sets the appropriate is bit if there is a request, and reads the priority level. interrupt is fro- zen from wr to rd . the word enabled onto the data bus during rd is: d7 d6 d5 d4 d3 d2 d1 d0 ieeeew2w1w0 w0 w2: binary code of the highest priority level requesting service. i: equal to ``1'' if there is an interrupt. this mode is useful if there is a routine command common to several levels so that the inta se- quence is not needed (saves rom space). another application is to use the poll mode to expand the number of priority levels to more than 64. reading the 8259A status the input status of several internal registers can be read to update the user information on the system. 16
8259A notes: 231468 22 1. master clear active only during icw1. 2. freeze is active during inta and poll sequences only. 3. truth table for a d-latch. c d q operation 1 di di follow 0 x qn-1 hold figure 9. priority cellesimplified logic diagram the following registers can be read via ocw3 (irr and isr or ocw1 [ imr ] ). interrupt request register (irr): 8-bit register which contains the levels requesting an interrupt to be ac- knowledged. the highest request level is reset from the irr when an interrupt is acknowledged. (not af- fected by imr.) in-service register (isr): 8-bit register which con- tains the priority levels that are being serviced. the isr is updated when an end of interrupt command is issued. interrupt mask register: 8-bit register which con- tains the interrupt request lines which are masked. the irr can be read when, prior to the rd pulse, a read register command is issued with ocw3 (rr e 1, ris e 0.) the isr can be read, when, prior to the rd pulse, a read register command is issued with ocw3 (rr e 1, ris e 1). there is no need to write an ocw3 before every status read operation, as long as the status read corresponds with the previous one; i.e., the 8259A ``remembers'' whether the irr or isr has been pre- viously selected by the ocw3. this is not true when poll is used. after initialization the 8259A is set to irr. for reading the imr, no ocw3 is needed. the out- put data bus will contain the imr whenever rd is active and a0 e 1 (ocw1). polling overrides status read when p e 1, rr e 1 in ocw3. edge and level triggered modes this mode is programmed using bit 3 in icw1. if ltim e `0', an interrupt request will be recognized by a low to high transition on an ir input. the ir input can remain high without generating another in- terrupt. 17
8259A 231468 23 figure 10. ir triggering timing requirements if ltim e `1', an interrupt request will be recognized by a `high' level on ir input, and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued or the cpu interrupts is enabled to prevent a second inter- rupt from occurring. the priority cell diagram shows a conceptual circuit of the level sensitive and edge sensitive input circuit- ry of the 8259A. be sure to note that the request latch is a transparent d type latch. in both the edge and level triggered modes the ir inputs must remain high until after the falling edge of the first inta . if the ir input goes low before this time a default ir7 will occur when the cpu ac- knowledges the interrupt. this can be a useful safe- guard for detecting interrupts caused by spurious noise glitches on the ir inputs. to implement this feature the ir7 routine is used for ``clean up'' simply executing a return instruction, thus ignoring the inter- rupt. if ir7 is needed for other purposes a default ir7 can still be detected by reading the isr. a nor- mal ir7 interrupt will set the corresponding isr bit, a default ir7 won't. if a default ir7 routine occurs dur- ing a normal ir7 routine, however, the isr will re- main set. in this case it is necessary to keep track of whether or not the ir7 routine was previously en- tered. if another ir7 occurs it is a default. the special fully nest mode this mode will be used in the case of a big system where cascading is used, and the priority has to be conserved within each slave. in this case the fully nested mode will be programmed to the master (us- ing icw4). this mode is similar to the normal nested mode with the following exceptions: a. when an interrupt request from a certain slave is in service this slave is not locked out from the master's priority logic and further interrupt re- quests from higher priority ir's within the slave will be recognized by the master and will initiate interrupts to the processor. (in the normal nested mode a slave is masked out when its request is in service and no higher requests from the same slave can be serviced.) b. when exiting the interrupt service routine the software has to check whether the interrupt serv- iced was the only one from that slave. this is done by sending a non-specific end of interrupt (eoi) command to the slave and then reading its in-service register and checking for zero. if it is empty, a non-specific eoi can be sent to the master too. if not, no eoi should be sent. buffered mode when the 8259A is used in a large system where bus driving buffers are required on the data bus and the cascading mode is used, there exists the prob- lem of enabling buffers. the buffered mode will structure the 8259A to send an enable signal on sp /en to enable the buffers. in this mode, whenever the 8259A's data bus outputs are enabled, the sp /en output becomes active. this modification forces the use of software pro- gramming to determine whether the 8259A is a mas- ter or a slave. bit 3 in icw4 programs the buffered mode, and bit 2 in icw4 determines whether it is a master or a slave. 18
8259A cascade mode the 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. the master controls the slaves through the 3 line cascade bus. the cascade bus acts like chip selects to the slaves during the inta sequence. in a cascade configuration, the slave interrupt out- puts are connected to the master interrupt request inputs. when a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of inta . (byte 2 only for 8086/8088). the cascade bus lines are normally low and will con- tain the slave address code from the trailing edge of the first inta pulse to the trailing edge of the third pulse. each 8259A in the system must follow a sep- arate initialization sequence and can be pro- grammed to work in a different mode. an eoi com- mand must be issued twice: once for the master and once for the corresponding slave. an address de- coder is required to activate the chip select (cs) input of each 8259A. the cascade lines of the master 8259A are activat- ed only for slave inputs, non-slave inputs leave the cascade line inactive (low). 231468 24 figure 11. cascading the 8259A 19
8259A absolute maximum ratings * ambient temperature under bias 0 cto70 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5v to a 7v power dissipation 1w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics t a e 0 cto70 c, v cc e 5v g 10% symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 * v cc a 0.5v v v ol output low voltage 0.45 v i ol e 2.2 ma v oh output high voltage 2.4 v i oh eb 400 m a v oh(int) interrupt output high 3.5 v i oh eb 100 m a voltage 2.4 v i oh eb 400 m a i li input load current b 10 a 10 m a0v s v in s v cc i lol output leakage current b 10 a 10 m a 0.45v s v out s v cc i cc v cc supply current 85 ma i lir ir input load current b 300 m av in e 0 10 m av in e v cc * note: for extended temperature express v ih e 2.3v. capacitance t a e 25 c; v cc e gnd e 0v symbol parameter min typ max unit test conditions c in input capacitance 10 pf fc e 1 mhz c i/o i/o capacitance 20 pf unmeasured pins returned to v ss 20
8259A a.c. characteristics t a e 0 cto70 c, v cc e 5v g 10% timing requirements symbol parameter 8259A 8259A-2 units test conditions min max min max tahrl ao/cs setup to rd /inta v 00 ns trhax ao/cs hold after rd /inta u 00 ns trlrh rd pulse width 235 160 ns tahwl ao/cs setup to wr v 00 ns twhax ao/cs hold after wr u 00 ns twlwh wr pulse width 290 190 ns tdvwh data setup to wr u 240 160 ns twhdx data hold after wr u 00 ns tjljh interrupt request width (low) 100 100 ns see note 1 tcvial cascade setup to second or third 55 40 ns inta v (slave only) trhrl end of rd to next rd end of inta to next inta within 160 100 ns an inta sequence only twhwl end of wr to next wr 190 100 ns * tchcl end of command to next command 500 150 ns (not same command type) end of inta sequence to next 500 300 inta sequence. * worst case timing for tchcl in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085a e 1.6 m s, 8085a-2 e 1 m s, 8086 e 1 m s, 8086-2 e 625 ns) note: this is the low time required to clear the input latch in the edge triggered mode. timing responses symbol parameter 8259A 8259A-2 units test conditions min max min max trldv data valid from rd /inta v 200 120 ns c of data bus e 100 pf trhdz data float after rd /inta u 10 100 10 85 ns c of data bus tjhih interrupt output delay 350 300 ns max test c e 100 pf tialcv cascade valid from first inta v 565 360 ns c int e 100 pf min test c e 15 pf (master only) trlel enable active from rd v or inta v 125 100 ns c cascade e 100 pf trheh enable inactive from rd u or inta u 150 150 ns tahdv data valid from stable address 200 200 ns tcvdv cascade valid to valid data 300 200 ns 21
8259A a.c. testing input/output waveform 231468 25 a.c. testing: inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. a.c. testing load circuit 231468 26 c l e 100 pf c l includes jig capacitance waveforms write 231468 27 22
8259A waveforms (continued) read/inta 231468 28 other timing 231468 29 23
8259A waveforms (continued) inta sequence 231468 30 notes: interrupt output must remain high at least until leading edge of first inta . 1. cycle 1 in 8086, 8088 systems, the data bus is not active. data sheet revision review the following changes have been made since revision 2 of the 8259A data sheet. 1. the first paragraph of the poll command section was rewritten to clarify the status of the int pin. 2. a paragraph was added to the interrupt sequence section to indicate the status of the int pin during multiple interrupts. 3. a reference to plcc packaging was added. 4. all references to the 8259A-8 have been deleted. intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 intel corporation (u.k.) ltd., swindon, united kingdom; tel. (0793) 696 000 intel japan k.k., ibaraki-ken; tel. 029747-8511 printed in u.s.a./xxxx/1196/b10m/xx xx

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